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Free-to-air system for digital video broadcasting over satellite (DVB-S)
On-chip CPU Main CPU : Integrated high-performance MIPS32® 4Kc® Core
Real-time operating system
Application program interface (API)
Basic input/output system (BIOS)
200 MIPS at 167 MHz
MIPS™ I, MIPS™ II instruction set architectures; subset of MIPS™ III
4 KB instruction and data caches with two types of access
Sub CPU : Integrated high-performance MIPS32® 4Km® Core
Sub-CPU for MPEG AV and AV-sync decoding inside firmware
200 MIPS at 167 MHz
MIPS™ II instruction set architecture
4 KB instruction cache; 4 KB data cache; 8 KB scratch pad
Memory interface
Unified memory interface for CPU, MPEG decoder, display, and graphics
µPD61110
SDR-SDRAM (x 16-bit bus)
fMAX= 133 MHz frequency
8, 16, 32, 64 MB
µPD61111
DDR-SDRAM (x 16-bit bus)
fMAX= 133 MHz frequency
16, 32, 64 MB
External ROM interface for CPU object code and data
Normal, page, and burst ROM
NOR, NAND flash ROM
64 MB address space (max.)
Two pairs of chip select signals
Thirty-two 8- and 16-byte section filters
High-speed data output port for IEEE1394 interface
MPEG stream processor
NEC processor core for software architecture
One parallel port or one serial port for stream input
MPEG2 transport stream
100 Mbps (max.)
36 process identifier (PID) filters
One video
Two audio
One processor capacity reservation
32 general
Thirty-two 8- and 16-byte section filters
High-speed data output port for IEEE1394 interface
MPEG video decoder
MPEG2 main profile (MP) at main level (ML) decoding
MPEG2 and MPEG1 elementary stream
Audio decoder
MIPS32® 4Km® core
200 Dhrystone MIPS at 167 MHz
MPEG1 and MPEG2 layer 1 and 2 decoding
Pulse-code-modulated L/R audio output
Sony™-Phillips™ digital interface format (SPDIF) with IEC60958 digital output (Dolby™ Digital can be passed through to SPDIF)
Test tone and mixing
Bit-boundry block transfer
(BIT-BLT) graphics engine
Two-dimensional image data transferring
RGB 32-to-YCbCr 4:2:2 color conversion for on-screen display
Color expansion
Display
Four graphics planes
One background plane
One live video plane
Two on-screen display planes (1, 2, 4, 8 bits per pixel + RGB 15, 16, 32)
256-level alpha blending among four planes
Real-time scaling for live planes; 1/4 to 4x horizontal and vertical
Anti-flicker filter for on-screen display plane
Video encoder
(for analog TV)
NTSC, PAL, and SECAM formats
Closed captioning, teletext, wide screen scaling (WSS), copy generation management system (CGMS), video ID, and vectors per second (VPS) capabilities
Four digital-to-analog converters for conversion of cut before video submission (CBVS), Y/C (luma/chroma), RGB, YCbCr, and YPbPr video output
ITU-R BT.656 digital output
Peripherals
16550-compatible UART with two 16-byte FIFOs
Two smart card interfaces
One I2C port
Two system, day, and watchdog timers
Four timers supporting input capture timers and output compare timers
Clocked serial interface
General-purpose I/O
Infrared receiver
Process
0.13 µm CMOS process
Power supply voltage
VDD: 1.5 V internal and 3.3 V I/O
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Прошивка (firmware) для ресивера Lumax- DV 748
Прошивка 3.62_2118
Прошивка Ver3.63_2118
Прошивка Ver3.53_1101_2118
Программа заливки
Инструкция по вводу ключей
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